Semiconductor memory devices typically receive an external column command such as an external read command or an external write command after an active command is input and operations in response to the active command are then completed. Hereinafter, delay between an input of the active command and an input of the external column command is referred to as tRCD. An address input with the external column command is input after tRCD. However, it is possible for a semiconductor memory device such as a DDR2 SDRAM to set input timing of the external column command even before tRCD. The semiconductor memory device holds the external column command input before tRCD for a predetermined time and generates an internal column command, such as an internal read command or an internal write command, corresponding to the external column command after tRCD passes from the timing of the active command. The predetermined time between an input of the external column command and generation of the internal column command is referred to as additive latency (AL). An external address input with the external column command is also held for the additive latency (AL) and, then, an internal address corresponding to the external address is generated.
FIG. 1 is a timing diagram for a read operation of a semiconductor memory device.
In order to perform a read operation, a semiconductor memory device such as DDR2 SDRAM generates an internal read address RD_IADD and an internal read command IRD after the additive latency AL passes from the input timing of an external read command RD and an external address EXT_ADDR. After a predetermined time from generation of the internal read command IRD and the internal read address RD_IADD, the semiconductor memory device starts to read a valid data D0 to D3. The predetermined time between the generation of the internal read command IRD and the internal address RD_IADD and start of the read operation is referred to as column address strobe (CAS) latency CL. The semiconductor memory device starts to perform the read operation after the additive latency AL and the CAS latency CL from the input timing of the read command and the address. A value obtained by adding the CAS latency CL to the additive latency AL is referred as a read latency RL.
FIG. 2 is a timing diagram for a write operation of the semiconductor memory device.
In the case of a write operation, the semiconductor memory device generates an internal write command IWT and an internal write address WT_IADD and performs the write operation after a write latency WL from an input timing of a write command WT and an external address EXT_ADDR. The write latency WL is less by one clock than the read latency RL. That is, WL=RL−1=(AL+CL)−1.
FIG. 3 is a block diagram of a conventional internal address generator for use in a semiconductor memory device.
As shown, the internal address generator includes an input latch 10, an AL delay unit 20, a CL delay unit 30, and an output latch 40. The input latch 10 latches an external address EXT_ADD and outputs an internal address INT_ADD in response to a read/write signal RDWT. The read/write signal RDWT is activated when one of a read command RD and a write command WT is input. The AL delay unit 20 delays the internal address INT_ADD in response to an additive latency information signal AL<0:N> synchronized with a clock signal CLK to thereby output a read address RD_ADD. The CL delay unit 30 delays the read address RD_ADD in response to a CAS latency information signal CL<2:M> synchronized with a write clock CLKWT and outputs a write address WT_ADD. The write clock CLKWT is a clock signal activated when the write command WT is input. The output latch 40 selects one of the read address RD_ADD and the write address WT_ADD in response to a read drive signal IRDP and a write drive signal IWTP and outputs as a column address CA. The read drive signal IRDP is activated after the additive latency period added to input timing of the read command RD. The write drive signal IWTP is activated after the CAS latency period added to input timing of the write command WT. The additive latency information signal AL<0:N> and the CAS latency information signal CL<2:M> are multi-bit signals. Only the bit of the additive latency information signal AL<0:N> and the CAS latency information signal CL<2:M> corresponding to the additive latency AL and the CAS latency CL of the semiconductor memory device is activated.
FIG. 4 is a schematic circuit diagram of the input latch 10 shown in FIG. 3.
As shown, the input latch 10 includes one transmission gate TG1 and a latch 12. The transmission gate TG1 transmits the external address EXT_ADD in response to the read/write signal RDWT. The latch 12 latches an output of the transmission gate TG1 and outputs the internal address INT_ADD. When one of the read command RD and the write command WT is input, the read/write signal RDWT is activated as a logic high level. The transmission gate TG1 transmits the external address EXT_ADD in response to the read/write signal RDWT of the logic high level. The latch 12 latches the external address EXT_ADD from the transmission gate TG1 and outputs as the internal address INT_ADD.
The AL delay unit 20 and the CL delay unit 30 include a plurality of shift registers.
FIG. 5 is a schematic circuit diagram of the shift register included in the AL delay unit 20 and the CL delay unit 30 shown in FIG. 3.
As shown, the shift register transmits data input through a terminal A in response to a drive clock signal input through a terminal B and outputs output signals through terminals C and D. For example, in case of the AL delay unit 20, the shift register transmits the internal address INT_ADD in response to the clock signal CLK. In case of the CL delay unit 30 transmits the read address RD_ADD in response to the write clock CLKWT. The shift register included in the AL delay unit 20 and the CL delay unit 30 shown in FIG. 3 performs its operation and, therefore, consumes power as long as the drive clock signal is input. However, there are some occasions that the shift register is not required to operate although the drive clock signal is input. For example, when an identical address is continuously input for several times, the shift register does not need to operate. Nevertheless, the shift register included the AL delay unit 20 and the CL delay unit 30 performs operation and, therefore, unnecessarily consumes power.